We are looking for a Physical Design to join us and help define and implement complex SOC in an advanced technology node.
She/he will develop flow and methodology, execute full RTL2GDS flow including synthesis, implementation and signoff for the most complex designs
She/he will work with the architecture and design team to build a full-chip floorplan includes portioning and power grid, provide static timing constraints for block and top-level, optimize block-level and top-level physical design to meet area and power specification
About Us
Our group is responsible for the development of NeuReality next generation SoC for AI Compute. The development starts from product definition through architecture, design, verification and physical design implementation.
The complex SoC is a high-performance device running AI compute for vision and audio processing, with technologies from multi-disciplines.
Requirements
- 3+ years’ experience with RTL2GDS flow
- BSC/MSC in Electrical/Computer engineering from research universities.
- Good understanding on STA principals
- Understand Synthesis, place and route flow
- Knowledge and experience in physical verification
- Experience in advanced nodes
Advantages
- Top-level implementation and signoff
- Experience with DFT
- Scripting skills TCL/Python
Caesarea Main Office: 14 Tarshish Street, Industrial Park Caesarea 3079559, Israel
+972 74-7023333
